Soy Mikel Fernandez, ingeniero informático por la Facultad de Informática de Barcelona (UPC) con el master "Computer Architecture, Systems and Networks" (CANS) del departamento de arquitectura de computadores (DAC). Actualmente trabajo en el Barcelona Supercomputing Center (BSC) en el grupo Computer architecture / Operating system interaface (CAOS), y también en Maspatechnologies.
Anteriormente he trabajado en Telefónica investigación y desarrollo (TID) y en Giesecke & Devrient (GyD Ibérica).
Conferencias
MASTECS Multicore Timing Analysis on an Avionics Vehicle Management Computer
R. Cruz, P. Harris, S. Thompson, C. Evripidou, T. Loveless, J. Reina, M. Fernandez, E. Mezzetti, F. Cazorla
11th Embedded Real Time Systems(ERTS 2022)
Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study
Xavier Palomo, Mikel Fernandez, Sylvain Girbal, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla, Laurent Rioux
32nd Euromicro Conference on Real-Time Systems (ECRTS 2020)
On the reliability of hardware event monitors in MPSoCs for critical domains
Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Enrico Mezzetti, Jaume Abella, Mikel Fernandez, Guillem Bernat, Francisco J. Cazorla
Proceedings of the 35th Annual ACM Symposium on Applied Computing (SAC 2020)
STT-MRAM for real-time embedded systems: performance and WCET implications
Kazi Asifuzzaman, Mikel Fernandez, Petar Radojkovic, Jaume Abella, Francisco J. Cazorla
Proceedings of the International Symposium on Memory Systems Proceedings of the International Symposium on Memory Systems (MEMSYS 2019)
Multicore Early Design Stage Guaranteed Performance Estimates for the Space Domain
Mikel Fernandez, Gabriel Fernandez, Jaume Abella, Francisco J. Cazorla
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE 2019)
MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding
Enrique Díaz, Mikel Fernandez, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernádez, Jaume Abella, Francisco J. Cazorla
Ada Europe 2017 - 22nd International Conference on Reliable Software Technologies (AE2017)
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application
Enrico Mezzetti, Mikel Fernandez, Alen Bardizbanyan, Irune Agirre, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla
23rd IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2017)
Probabilistic Timing Analysis on Time-Randomized Platforms for the Space Domain
Mikel Fernandez, David Morales, Leonidas Kosmidis, Alen Bardizbanyan, Ian Broster, Carles Hernandez, Eduardo Quinones, Jaume Abella, Francisco Cazorla, Paulo Machado and Luca Fossati
20th Design, Automation, and Test in Europe (DATE 2017)
pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems
Mladen Slijepcevic, Mikel Fernandez, Carlen Hernandez, Jaume Abella, Eduardo Quińones, Francisco J. Cazorla
19th Euromicro Conference on Digital Systems Design (DSD 2016)
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis
F. Cazorla, Abella, J., Andersson, J., Vardanega, T., Vatrinet, F., Bate, I., Broster, I., Azkarate-askasua, M., Wartel, F., Cucu-Grosjean, L., Cros, F., Farrall, G., Gogonel, A., Gianarro, A., Triquet, B., Hernandez, C., Lo, C., Maxim, C., Morales, D., Quiñones, E., Mezzetti, E., Kosmidis, L., Agirre, I., Fernandez, M., Slijepcevic, M., Conmy, P. Ryan, and Talaboulma, W.
19th Euromicro Conference on Digital System Design (DSD 2016)
Contention-aware performance monitoring counte support for real-time MPSoCs
Javier Jalle, Mikel Fernandez, Jaume Abella, Jan Andersson, Mathieu Patte, Luca Fossati, Marco Zulianello, Francisco J. Cazorla
11th IEEE Symposium on Industrial Embedded Systems (SIES 2016)
Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems
David Trilla, Javier Jalle, Mikel Fernandez, Jaume Abella, Francisco J. Cazorla
22nd IEEE Real-Time Embedded Technology & Applications Symposium (RTAS 2016) (Slides)
Bounding Resource Contention Interference in the Next-Generation Microprocessor (NGMP)[alt link]
Javier Jalle, Mikel Fernandez, Jaume Abella, Jan Andersson, Mathieu Patte, Luca Fossati, Marco Zulianello, Francisco J Cazorla
8th European Congress on Embedded Real Time Software and Systems (ERTS 2016)
Assessing the Suitability of the NGMP Multi-core Processor in the Space Domain
Mikel Fernandez, Roberto Gioiosa, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla
International Conference on Embedded Software (EMSOFT 2012)
Automatic generation of application-specific hardware accelerators on OpenSPARC
Cecilia Gonzalez-Alvarez, Mikel Fernandez, Daniel Jiménez-González, Carlos Alvarez and Xavier Martorell
International Symposium on Code Generation and Optimization (CGO 2011)
Workshops
Timing Properties of the LEON3-based GR712RC Board. Implications on Task Scheduling (Slides)
Francisco J. Cazorla, Mikel Fernandez, Jaume Abella, Eduardo Quiñones, Gabriel Fernandez, Marco Zulianello, Christophe Honvault, Luca Fossati
TEC-ED & SW Final Presentation Days, December 2013
Measuring inter-task interferences in the NGMP
Francisco J. Cazorla, Mikel Fernandez, Roberto Gioiosa, Eduardo Quiñones, Marco Zulianello, Luca Fossati
[Abstract], 5th ESA Workshop on Avionics, Data, Control and Software Systems (ADCSS 2011)
Automatic Generation and Testing of Application Specific Hardware Accelerators on a New Reconfigurable OpenSPARC Platform
Cecilia Gonzalez-Alvarez, Mikel Fernandez, Daniel Jiménez-González, Carlos Alvarez and Xavier Martorell
HiPEAC WRC 2011
Posters
Assessing the effect on inter-task interferences in real multicores
Gabriel Fernandez, Mikel Fernandez, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla
ACACES 2013
Memoria de mi master thesis:
Memoria de mi PFC:
MASTECS H2020 project number 878752 (2019 - 2022)
ESA-EFL: Assessment of the Implementation of the EFL Time-Randomised Cache in the NGMP Architecture ESA Project number 4000116210/NL/FE/as (2016 - 2017) (Abstract)
PROXIMA FP7-ICT project number 611085 (10/2013 - 10/2016)
Emulators of Future NGMP Multicore Processors (Abstract) (Slides)
PROARTIS for Space (P4S) ESA ITT Ref AO/1-7646/13/NL/JK (01/2014 - 04/2015)
Multi-Core architectures - Cache structure optimisation for better RT performance (Multi-core PMCs: analysis and architectural definition) (Proposal of PMCs for tracking worst-case behaviour in multicores: the case of the NGMP ) ESA project number RFP PFL-PTE/HK/mo/789.2013 (11/2013 - 04/2014)
parMERASA FP7-ICT project number 287519 (10/2011 - 09/2014)
Proartis FP7-ICT project number 249100 (02/2010 - 07/2013)
Organización y participación en Mixed-Criticality Cluster workshop (MCC 2016) [PDF].
MASTECS H2020 European ProjectIntroducing the first certification-ready multicore timing analysis solution
PROXIMA processors for space applications win HiPEAC Technology Transfer Award Web (PDF)
PROXIMA presents research to leading European technology companies Web (PDF) (PDF)
PROXIMA: técnicas probabilisticas y aleatorización para analizar el tiempo de respuesta de sistemas críticosWeb (PDF) (PDF)
Participación en proyectos:
Videos relacionados con mi trabajo en TID: